Die FPGA-Kochecke

FPGA-Projekte an Universitäten

• TU Hamburg-Harburg, Arbeitsbereich Nachrichtentechnik
  FPGA-Platine und Anwendungen (Datenübertragung mit einem Laserpointer, Radar-Puls-Doppler) im Rahmen der praxisorientierten Aktivität Hobbythek
  http://www.et2.tu-harburg.de/lehre/Hobbythek/fpga.htm
  
  
• FH Nürnberg
  Entwicklung eines parametrisierbaren Mikrocontrollers in VHDL mit anschließendem Rapid Prototyping auf einem FPGA-Emulator
  unter Verwendung eines PROmetheus FPGA-Emulators der Firma Mikroelektronik Design Dresden (MDD)
  http://www.nf.fh-nuernberg.de/labors/me1/projekte/paramic/
  
  
• http://www.dnai.com/~jfox/fpgakit.htm
  
  
• FPGA-Projekte von Scott A. Hauck, ECE Department, Northwestern University
  
  
• RUBIN (Rule-Based Intelligent Networks) Projekt des Institut fuer Technische Informatik der Medizinische Universitaet zu Luebeck
  RUBIN is a router design targeting to break this ambivalence as it offers a configurable and fast implementation for a wide variety of fault tolerant and adaptive routing algorithm. The key approach of RUBIN is a rule-based representation of algorithm where the router's behavior could be completely exchanged by reloading rule bases.
  Derzeit Prototyp mit 4 XILINX-FPGAs (3 * XC40150XV + 1 * XC40250 XV)
  WWW: http://www.iti.mu-luebeck.de/RBR/rbr-www/
  
  
• Projekte des Northwest Laboratory for Integrated Systems der University of Washington
  • RaPiD:Reconfigurable Pipelined Datapath
    RaPiD is a coarse-grained high-performance FPGA architecture that allows deeply pipelined computational datapaths to be constructed dynamically from a mix of functional units.
  • Asynchronous Circuits
    Survey of current asynchronous design methodologies, as well as the first FPGA for asynchronous circuits.
  • Triptych/Montage FPGA Architectures
    Development of the Triptych and Montage FPGA architectures, architectures with improved densities over current commercial FPGAs.
  • Multi-FPGA Systems & Rapid-Prototyping
    Development of the Springbok Rapid-Prototyping System for Board-Level Designs, as well as partitioning, pin assignment, and routing topology work for general multi-FPGA systems.
  • Emerald
    An Architecture-Adaptive Toolset for FPGAs
  
  
  

16 bit minimal processor
klee@mistress.informatik.unibw-muenchen.de (Herbert Kleebauer)
Fakultaet fuer Informatik, Universitaet der BW Muenchen
 
As an exercise for our students we have developed and implemented a 
16 bit minimal processor. The processor can address 64 kByte and 
supports hardware interrupts. It is built with 65 flip-flops and 
about 250 gates. The documentation and schematics can be found at 
ftp://137.193.64.130/pub/mproz/

Don Golding wrote in message <7fcu4r$hd6@dfw-ixnews6.ix.netcom.com>...
>I want to implement a Forth Engine like the RTX2000 on an FPGA.  Any help
>would be appreciated.

One superb example is the MSL16 microprocessor.  See Leong, P.H.W, P.K.
Tsang, and T.K. Lee, "A FPGA based Forth microprocessor", pp. 254-255, in
Proc. IEEE Symp. on FPGAs for Custom Computing Machines 1998, and at
http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, and Paul Lee Wai Lun's
thesis and presentation, "FPGA Implementation of a Forth Processor", at
http://home.hkstar.com/~wail/project-7260/project.htm.