Die FPGA-Kochecke

FPGA-Projekte an Universitäten

16 bit minimal processor
klee@mistress.informatik.unibw-muenchen.de (Herbert Kleebauer)
Fakultaet fuer Informatik, Universitaet der BW Muenchen
As an exercise for our students we have developed and implemented a 
16 bit minimal processor. The processor can address 64 kByte and 
supports hardware interrupts. It is built with 65 flip-flops and 
about 250 gates. The documentation and schematics can be found at

Don Golding wrote in message <7fcu4r$hd6@dfw-ixnews6.ix.netcom.com>...
>I want to implement a Forth Engine like the RTX2000 on an FPGA.  Any help
>would be appreciated.

One superb example is the MSL16 microprocessor.  See Leong, P.H.W, P.K.
Tsang, and T.K. Lee, "A FPGA based Forth microprocessor", pp. 254-255, in
Proc. IEEE Symp. on FPGAs for Custom Computing Machines 1998, and at
http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, and Paul Lee Wai Lun's
thesis and presentation, "FPGA Implementation of a Forth Processor", at

Letzte Änderung: 1.4.2005; Die Liste erhebt keinen Anspruch auf Vollständigkeit.

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