Das FPGA-Kochbuch

Listing 4:   entity VOLLADD is
                port (A,B,C:      in  bit;
                      CRY,SUM:    out bit);
             end VOLLADD;

             architecture STRUKTUR of VOLLADD is
             signal X1,X2,X3: bit;

             component HALBADD
                port (A,B:      in  bit;
                      CRY,SUM:  out bit);
             end component;

             component ODERGAT
                port (I1,I2:    in  bit;
                      OUT1:     out bit);
             end component;

             begin
                u1: HALBADD port map(A,B,X1,X2);
                u2: HALBADD port map(X2,C,X3,SUM);
                u3: ODERGAT port map(OUT1=>CRY,I1=>X1,I2=>X3);
             end STRUKTUR;